A layout specifies the components of an integrated circuit (IC) and their positions within the IC. A pcell is a parametrized cell representing a part or a component of the IC. A pcell may include a collection of shapes. Each shape may belong to one of several technology layers of the IC. Each pcell layout, not an individual shape within the pcell, may have certain pcell parameter values associated with it. The pcell parameter values may be used as input data for a pcell program which can be executed to generate a pcell layout.
A pcell may, for example, be implemented in the form of an executable script. A pcell usually includes a set of parameters for defining properties of the components represented by the pcell. A layout may include one or more than one instance of one or more than one pcell. For example, a first instance of a pcell may represent a first component, e.g., a first subcircuit, and a second pcell may represent another component of the same IC.
Current methods of process migration of layouts with pcells do not necessarily preserve pcell connectivity in the migrated layout Known automatic methods of connectivity correction do not necessarily fix all violations and a manual correction effort may be needed. This effort can be substantial.
Referring to FIGS. 1 and 2, an example of a source layout before (FIG. 1) and after (FIG. 2) a cell swapping operation is described. The layout 10 may comprise a plurality of electronic components such as conductors, inductors, capacitors, and semiconductor based components. In the present example, the layout comprises one or more conductors 14 arranged in a first layer and one or more conductors 16 arranged in a second layer of the integrated circuit. A pcell 12 may specify one or more portions of the shown circuitry, e.g., the conductors 14 and 16, or portions thereof. For instance, each of the conductors 14 and 16 may have a segment defined by the pcell 12.
The aim of a process migration may be seen in converting a layout from one technology node to another. In this process, the layout may have to be modified to meet design rules of the target technology while preserving layout connectivity and minimizing layout changes. The design rules may specify conditions such as minimum distances between conductors, minimum or maximum widths of conductors, and other length or size constraints.
Custom layouts may be created using pcells. A pcell may, for example, be implemented as a script for generating a layout based on user-defined parameters. During migration, a source pcell may be replaced by a target pcell. This process is known as cell swapping. In many cases, cell swapping may introduce connectivity violations that may require manual attention. Notably, it may be insufficient to adapt the values of the parameters of a pcell.
For instance, now turning to FIG. 2, replacing the pcell 12 of the source technology by a corresponding pcell 12′ of the target technology may result in discontinuities of, e.g., the conductors 16 in a region 18 or in shorts between components defined by the pcell 12′ and components not defined by the pcell 12′ in region 20.
FIG. 3 shows a flowchart of an example of a known method of converting a layout from a source technology to a target technology. The method may use as input data, the layout relating to the source technology (also referred to herein as the source technology layout or the source layout), a layer map, a pcell map, and a set of design rules as specified in, e.g., a design rule manual (DRM). The source layout may comprise one or more than one layers. A layer is a flat region in which components of the integrated circuit may be arranged. The integrated circuit may, however, comprise components located in more than one layer. Several layers may be stacked atop each other to form the integrated circuit. The layer map may indicate for each layer of the source layout a corresponding layer of the transformed layout. The correspondence between source layers and target layers may be one-to-one. Each source layer may thus have associated with it precisely one target layer and vice versa. The ordering of the layers, i.e., the sequence in which they are stacked, may however be different in the source layout compared to the target layout.
The pcell map may indicate for each pcell of the source layout a target pcell into which the source pcell is to be transformed. The pcell mapping thus defined is not necessarily bijective. For instance, two different source pcells may be mapped onto the same target pcell.
In a first block 3.1, the source layout may be pre-processed. For example, the layers of the source layout (the source layers) may be rearranged in accordance with the layer map. The source layers may thus be reordered in accordance with the target technology. Furthermore, the pcells of the source layout may be replaced by their counterpart pcells as specified by the pcell map (block 3.2). A legalization procedure (block 3.3) may then be applied to the modified source layout resulting from blocks 3.1 and 3.2. The legalization procedure may include determining geometric parameters of the source layout in accordance with the target design rules. The blocks 3.1, 3.2, and 3.3 may result in connectivity violations such as shorts or opens. Some, but not necessarily all of these violations may be detected and fixed automatically. The remaining connectivity violations may be fixed manually (block 3.5). Blocks 3.1 to 3.5 may thus transform the source layout into the target layout.
The input data, the operations carried out on the input data, and the resulting output data for the various blocks shown in FIG. 3 may be summarized as follows:
Preprocessing (block 3.1). Input: layout, layer map. The layer map may be used to rename source technology layers to target. Other operations such as scaling may be performed. Output: preprocessed layout.
Swapping pcells (block 3.2). Input: preprocessed layout, pcell map. Pcell map is used to swap source pcells with target ones. Output: preprocessed layout with swapped pcells and added connectivity violations.
Legalization (block 3.3). Input: preprocessed layout with swapped pcells and connectivity violations, DRM. DRM is used to create constraints in constraint graph based algorithm. Output:
migrated layout with connectivity violations.
Detecting and fixing shorts/opens (automatically) (block 3.4). Input: migrated layout with connectivity violations. Some violations are not fixed automatically. Output: migrated layout with connectivity violations.
Fixing remaining shorts/opens manually (block 3.5). Input: migrated layout with connectivity violations. Output: migrated layout.